Technology scaling has been the driving force for the semiconductor industry in achieving higher performance and lower energy per switching in integrated circuit design. The cost paid with respect to traditional complementary metal oxide semiconductor (CMOS) scaling is the exponential increase in leakage power and process variations (PV), which are causing an increasingly negative effect on circuit performance and robustness. Since these internal fluctuations are unavoidable, it is critical to design circuits and systems which are robust to process variations. As is known, process variation is a statistical description of fluctuations in process outputs, in this case, fluctuations in the outputs of a semiconductor fabrication process.
However, the first step in designing these kinds of circuits is to sense process variations. Sensing process variations will not only give information about how the circuits should be calibrated to compensate variations but also provide feedback on what is going wrong during manufacturing.
The idea in sensing the process variation is to use the leakage current due to its high sensitivity to process variations. Different solutions for the same problem have been suggested in the literature. In T. Kuroda, et al., “A 0.9V 150 Mhz 10 mW 4 mm2 2-D discrete cosine transform core processor with variable-threshold-voltage scheme,” ISSCC, pp. 166-167, February 1996, the disclosure of which is incorporated by reference herein, a leakage sensing circuit was proposed to monitor variable threshold voltage CMOS systems. However, the proposed circuit which is shown in FIG. 1(a) suffers from low sensing gain and area overhead for the process variation independent bias voltage generator circuit.
Another circuit for monitoring PV was proposed in M. M. Griffin, et al., “A process-independent, 800-MB/s DRAM byte-wide interface featuring command interleaving and concurrent memory operation,” IEEE Journal of Solid-State Circuits, Vol. 33, Issue 11, pp. 1741-1751, November 1998, the disclosure of which is incorporated by reference herein, and shown in FIG. 1(b). Nevertheless, this circuit needs a PV independent current reference (IREF) which increases the area. Moreover, the diode-connected NMOS limits the voltage swing on VSEN which decreases the sensitivity of the circuit.
In another work, a sensor circuit is described in C. H. Kim, et al., “Self Calibrating Circuit Design for Variation Tolerant VLSI Systems,” IOLTS, pp. 100-105, July 2005, the disclosure of which is incorporated by reference herein. However, as shown in FIG. 1(c), the need for PV insensitive bias current and voltage requires a large area and makes this circuit impractical.
Ring oscillators (RO) were suggested as process variation sensors in M. Bhushan, et al., “Ring Oscillators for CMOS Process Tuning and Variability Control,” IEEE Transactions on Semiconductor Manufacturing, Vol. 19, No. 1, pp. 10-18, February 2006, the disclosure of which is incorporated by reference herein. However, due to the area overhead of ring oscillators, it is impractical to place a large number of ROs across the chip (integrated circuit or IC) for better resolution. Moreover, since the process variations are averaged out through the inverter chain in ROs, local process variations can not be observed with ROs.
N. Jayakumar, et al., “A Self-adjusting Scheme to Determine the Optimum RBB by Monitoring Leakage Currents,” DAC, pp. 43-46, June 2005, the disclosure of which is incorporated by reference herein, suggests another leakage sensing mechanism which is based on monitoring the capacitor charge leaking through an negative-channel MOS (NMOS) device. The required capacitor bank and the body bias voltage, which needs triple well technology, make this mechanism not feasible.